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71M6545/71M6545H Data Sheet
Name
Location
Rst Wk Dir
Description
PLS_INTERVAL[7:0]
PLS_INV
PORT_E
PRE_E
PREBOOT
RCMD[4:0]
RESET
RFLY_DIS
RMT2_E
RMT4_E
RMT6_E
RMT_RD[15:8]
RMT_RD[7:0]
RTCA_ADJ[6:0]
RTC_FAIL
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
RTC_RD
RTC_SBSC[7:0]
210B[7:0]
210C[0]
270C[5]
2704[5]
SFRB2[7]
SFR FC[4:0]
2200[3]
210C[3]
2709[3]
2709[4]
2709[5]
2602[7:0]
2603[7:0]
2504[6:0]
2890[4]
289B[2:0]
289C[7:0]
289D[7:2]
289D[1:0]
2890[6]
2892[7:0]
0
0
0
0
–
0
0
0
0
0
40
0
4
0
0
0
0
–
0
0
0
0
–
0
0
0
0
0
–
0
4
0
0
0
0
–
R/W
R/W
R/W
R/W
R
R/W
W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
Determines the Interval time. The time between FIFO outputs is
PLS_INTERVAL[7:0] *4*203ns. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and
pulses are output as soon as the CE issues them. Assuming a that the CE code is
written to generate 6 pulses in one integration interval, when the FIFO is enabled (i.e.,
PLS_INTERVAL[7:0] ≠ 0) and SUM_SAMPS = 2520, PLS_INTERVAL[7:0] must be
written with 81 so that the six pulses are evenly spaced in time over the integration
interval and the last pulse is issued just prior to the end of the interval.
Inverts the polarity of WPULSE, VARPULSE, XPULSE, and YPULSE. Normally, these
pulses are active low. When inverted, they become active high.
Enables outputs from the DIO0-DIO14 pins. PORT_E = 0 blocks the momentary output
pulse that occurs when DIO0-DIO14 are reset on power up.
Enables the 8x pre-amplifier.
Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD , the 71M6545/H issues a command
to the appropriate remote sensor. When the command is complete, the 71M6545/H
clears RCMD.
When set, causes a reset.
Controls how the 71M6545/H drives the power pulse for the 71M6xxx. When set, the
power pulse is driven high and low. When cleared, it is driven high followed by an
open circuit flyback interval.
Enables the remote interface.
Response from remote read request.
Register for analog RTC frequency adjustment.
Indicates that a count error has occurred in the RTC and that the time is not
trustworthy. This bit can be cleared by writing a 0.
RTC adjust. See 2.5.4 Real-Time Clock (RTC) .
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
RTC adjust. See 2.5.4 Real-Time Clock (RTC) .
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
Freezes the RTC shadow register so it is suitable for MPU reads. When RTC_RD is
read, it returns the status of the shadow register:
0 = up to date, 1 = frozen.
Time remaining since the last 1 second boundary. LSB=1/128 second.
94
v2
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